The continued need for increasingly complex electronic circuits has lead to corresponding demands for simulators that can quickly simulate, to a high degree of accuracy, the complex interactions occurring within a complex circuit. Circuits are growing more and more complex with “System On Chip” (SoC) designs implemented that contain hundreds of millions of logic circuits.
Systems on a chip (SoCs) that include programmable processors are in widespread use, and using a virtual processor model is particularly advantageous in designing such SoCs. The bus design for such circuits is often obtained as part of a pre-defined design for use in designing a SoC.
Virtual bus models for circuits containing one or more programmable processors are detailed and therefore non-trivial to design. As a result, vendors such as VaST Systems Technology Corporation of Sunnyvale, Calif., provide pre-defined virtual processor models for many popular processors.
Many SoCs, however, are designed to include one or more custom, programmable processors, e.g., processors that might be similar to an available processor design, but have different word lengths, different operations, and so forth.
Various methods are currently used for the simulation of complex electronic circuits. The circuit to be simulated is normally described in a top down manner using a hardware description language (HDL) such as VHDL or Verilog. VHDL is described, for example, in IEEE Computer Society “IEEE Standard VHDL Language Reference Manual” New York, USA, June 1994, and Verilog is described, for example, in IEEE Computer Society, “IEEE Standard Hardware Description Language Based on the Verilog Hardware Description Language, New York, USA, 1996, each of which are incorporated by reference herein in pertinent parts. These are commonly referred to as synthesis based approaches as the same circuit description may also be used in the generation of the physical circuit layout. As circuit complexity continues to increase, there is a trend to move away from these synthesis-based approaches to ones using higher level hardware descriptions usually based on languages such as behavioral VHDL, Verilog with behavioral extensions, C and C++. An example of such a high-level simulation language is SystemC which uses C++ as a system description language.
Once a circuit to be simulated is described in one of the above languages, simulators are available for simulating operation of the hardware device. For example, standard C++ compilers together with SystemC libraries can be used to simulate SystemC coded models. Complex circuits are often constructed using a high level language such as Verilog, SystemC, VHDL, or the like, and extensively simulated using cycle accurate simulators to verify operation. Subsequently, after satisfactory verification, the model, if coded using a synthesizable HDL, may be directly synthesized into lower level circuit designs. The model is extremely useful in allowing verification of the design and target software to proceed long before and even after the design has been implemented.
Bus structures are used in digital systems to connect processors with memory, peripheral devices, etc. There are many standard bus protocols known for bus structures, e.g., PCI and the AMBA bus protocols by ARM Holdings PLC of Cambridge, England including AMBA AHB, AMBA APB, AMBA AHB_Lite, IbBus, U-Bus, and others. There are many interconnect protocols, such as the Sun Host to PCI Bridge protocol (HPB) by Sun Microsystems, Inc. of Menlo Park, Calif.
New bus protocols have become available that provide for much more complex behavior than older bus systems. Such more complex behaviors include the ability of a master device to execute several transactions at a time, and for slave devices to receive and process several transactions at a time. Furthermore, bus protocols have recently been developed for incorporating complex interconnects between devices, e.g., interconnects that include switching fabrics. In such an architecture, several master devices and several slave devices may connect to an interconnect circuit each using, for example, a bus structure that supports several transactions at once. The interconnect includes switching elements, buffers, etc., that provide for interconnecting the master devices and slave devices, including issuing and/or processing several transactions at once.
One example of such a bus structure is the AMBA® AXI Protocol (hereinafter AXI protocol, or simply AXI) as defined, for example, in the published specification of AXI, titled “AMBA® AXI Protocol Specification, V1.0, by ARM Ltd., also known as the AMBA specification.
Accordingly, there is a need for methods, systems, and computer program products for simulating bus structures. What is also needed are methods, systems, and computer program products to model such bus structures and their connections to interconnect circuits.
Some programmable processor types, however, contain many structures in common. Furthermore, programmable processors tend to fall into families that have aspects in common. Accordingly, what is needed are methods, systems, and computer program products which are able to simulate and model bus structures for system designs incorporating one or more programmable processors.
Thus there is a need for a customizable virtual bus model for system designs including one or more programmable processors, and for a method and apparatus for modifying a provided virtual bus model.